发明名称 |
Method and circuit for DisplayPort video clock recovery |
摘要 |
A method and a circuit are described for recovery of video clocks for a DisplayPort receiver. The disclosure includes two clock dividers, a direct digital synthesis (DDS), a fixed multiplier Phase-Locked Loop (PLL) on a DisplayPort video system. A DisplayPort receiver link clock is divided to a lower frequency as the input of the DDS which can lower the performance requirement on a DDS circuit. The output from a time stamp value indirectly controls a direct digital synthesis device, which then drives a PLL to generate the recovery clock signal. The technique is suitable for implementation on an integrated circuit and Field Programmable Gate array system. |
申请公布号 |
US8217689(B2) |
申请公布日期 |
2012.07.10 |
申请号 |
US20100675106 |
申请日期 |
2010.01.19 |
申请人 |
YANG LU;WANG SIBING;ZHANG XIAOQIAN;INTEGRATED DEVICE TECHNOLOGY, INC. |
发明人 |
YANG LU;WANG SIBING;ZHANG XIAOQIAN |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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