发明名称 Semiconductor memory device which includes memory cell having charge accumulation layer and control gate
摘要 A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.
申请公布号 US8219744(B2) 申请公布日期 2012.07.10
申请号 US201113301969 申请日期 2011.11.22
申请人 SUZUKI TAKAHIRO;FUJISAWA SHINYA;HARA TOKUMASA;NISHIYAMA MASUJI;KABUSHIKI KAISHA TOSHIBA 发明人 SUZUKI TAKAHIRO;FUJISAWA SHINYA;HARA TOKUMASA;NISHIYAMA MASUJI
分类号 G06F12/02 主分类号 G06F12/02
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