发明名称 Memory controller to utilize DRAM write buffers
摘要 A method, an apparatus, and a computer program are provided to account for data stored in Dynamic Random Access Memory (DRAM) write buffers. There is difficulty in tracking the data stored in DRAM write buffers. To alleviate the difficulty, a cache line list is employed. The cache line list is maintained in a memory controller, which is updated with data movement. This list allows for ease of maintenance of data without loss of consistency.
申请公布号 US8219745(B2) 申请公布日期 2012.07.10
申请号 US20040002556 申请日期 2004.12.02
申请人 BELLOWS MARK DAVID;HASELHORST KENT HAROLD;HEAKENDORF RYAN ABEL;GANFIELD PAUL ALLEN;OZGUNER TOLGA;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 BELLOWS MARK DAVID;HASELHORST KENT HAROLD;HEAKENDORF RYAN ABEL;GANFIELD PAUL ALLEN;OZGUNER TOLGA
分类号 G06F12/00 主分类号 G06F12/00
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