发明名称 Low power clocking scheme for a pipelined ADC
摘要 Delay locked loops or DLLs are oftentimes employed in pipelined analog-to-digital converters (ADCs). Conventional DLLs, though, can consume an excessive amount of power. Here, a DLL is provided with a modified charge pump that allows for reduced power consumption.
申请公布号 US8217691(B2) 申请公布日期 2012.07.10
申请号 US20090645165 申请日期 2009.12.22
申请人 PENTAKOTA VISVESVARAYA A.;TEXAS INSTRUMENTS INCORPORATED 发明人 PENTAKOTA VISVESVARAYA A.
分类号 H03L7/06;H03L7/093 主分类号 H03L7/06
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