发明名称 SEMICONDUCTOR DEVICE
摘要 A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
申请公布号 US2012168875(A1) 申请公布日期 2012.07.05
申请号 US201213421010 申请日期 2012.03.15
申请人 TAMARU MASAKI;NAKANISHI KAZUYUKI;NISHIMURA HIDETOSHI;PANASONIC CORPORATION 发明人 TAMARU MASAKI;NAKANISHI KAZUYUKI;NISHIMURA HIDETOSHI
分类号 H01L27/088 主分类号 H01L27/088
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