| 摘要 |
Provided are a DDR controller, and a method and chip for implementing same, which are suitable to be used in the field of DDR controller technology.The method comprises the following steps: analysing a plurality of cached commands at the same time (S501); prejudging the relationship between the Bank and Row of an address accessed by each analysed command and the Bank and Row of an address of a command being executed; and sending a PRECHARGE command and an ACTIVE command in advance. According to the above technical solution, the pre-charge command and active command which were formerly sent in series can be carried out in advance so as to be concealed in parallel during the READ, or WRITE, etc. period, making the best use of the bandwidth of the DDR device. |
