发明名称 OPERATIONAL AMPLIFIER WITH LATCHING STATE SUPPRESSION
摘要 An amplifier circuit (200) comprises an amplifier stage having at least one input terminal (INa,INb) for receiving an input signal (Vin) and at least one output terminal (OUTa,OUTb) for providing an output signal (Vout). The amplifier circuit further comprises a load stage (215) comprising at least one load node (A, B). The amplifier circuit further comprises a control block (135) for providing a control signal (Con) to the load stage according to the output signal, and first biasing means (130) for providing a first bias current (IBIASu) to each load node (A, B). The load stage comprises second biasing means (125a, 125b) for providing at least one second bias current (IBIASd, IBIASf) to each load node and regulation means (120a, 120b) for providing a regulation current (IREG) to each load node according to the control signal.
申请公布号 WO2012089810(A1) 申请公布日期 2012.07.05
申请号 WO2011EP74235 申请日期 2011.12.29
申请人 ACCENT S.P.A.;PELLEGRINI, AURELIO 发明人 PELLEGRINI, AURELIO
分类号 H03F3/45 主分类号 H03F3/45
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