发明名称 |
Method and Apparatus for Delaying Write Operations |
摘要 |
An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit to the DRAM a first code to indicate that first data is to be written to the DRAM. The first code is to be sampled by the DRAM and held by the DRAM for a first period of time before it is issued inside the DRAM. The interface is further to transmit the first data that is to be sampled by the DRAM after a second period of time has elapsed from when the first code is sampled by the DRAM. The interface is further to transmit a second code, different from the first code, to indicate that second data is to be read from the DRAM. The second code is to be sampled by the DRAM on one or more edges of the external clock signal. |
申请公布号 |
US2012173811(A1) |
申请公布日期 |
2012.07.05 |
申请号 |
US201213421753 |
申请日期 |
2012.03.15 |
申请人 |
BARTH RICHARD M.;WARE FREDERICK A.;STARK DONALD C.;HAMPEL CRAIG E.;DAVIS PAUL G.;ABHYANKAR ABHIJIT M.;GASBARRO JAMES A.;NGUYEN DAVID |
发明人 |
BARTH RICHARD M.;WARE FREDERICK A.;STARK DONALD C.;HAMPEL CRAIG E.;DAVIS PAUL G.;ABHYANKAR ABHIJIT M.;GASBARRO JAMES A.;NGUYEN DAVID |
分类号 |
G06F12/00;G11C7/10;G11C7/12;G11C11/4096 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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