| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of reducing time for IDDQ test and the like. <P>SOLUTION: In a semiconductor integrated circuit 1 in which a CMOS logic circuit 10 is integrated, an output logic value control circuit 20 is provided between a plurality of output stage CMOS devices 12 of the CMOS logic circuit 10 and a plurality of output terminals 32 for outputting a signal to the outside. The output logic value control circuit 20 is composed of a plurality of logical operators 21 of two-input one-output that is provided corresponding to the plurality of output stage CMOS devices 12, respectively. While a logical value output by the output stage CMOS device 12 is input into one input port, a control signal 22 is input into the other input port. The logical operator 21 can fix the logical value of an output port at either High or Low when the control signal 22 is fixed at either High or Low. <P>COPYRIGHT: (C)2012,JPO&INPIT |
