| 摘要 |
<P>PROBLEM TO BE SOLVED: To make release timing of a load buffer early by reducing a load between a cache memory and a main storage device. <P>SOLUTION: A vector operation processing apparatus includes a load buffer management section 31 which ensures a buffer region M2 of vector data when a vector load instruction to be executed speculatively is issued, a cache processing section 4 which reads element data from a cache memory M1 or a main storage device 9 on the basis of a memory access request and stores the read element data into the buffer region M2, and a vector processing section 6 which releases the buffer region M2 after transferring the element data in the buffer region to a vector register M3 in the case where speculative execution is made successful, and releases the buffer region M2 without transferring the element data in the buffer region M2 to the vector register M3 in the case where the speculative execution is failed, on the other hand. In the case where the speculative execution is failed, the cache processing section 4 suppresses reading of the element data from the main storage device 9. <P>COPYRIGHT: (C)2012,JPO&INPIT |
