发明名称 Method and System for Generating a Placement Layout of a VLSI Circuit Design
摘要 A method and a system for generating a placement layout is disclosed. The method includes receiving one or more user provided schematic with circuit data, placement parameters of circuit elements, default values, and user specified function calls and variables for calculating placement parameters; evaluating variables and function calls to discrete placement parameters; evaluating justification values and adjusting relative parameter values; calculating absolute placement coordinates for all cells from relative placement parameters for each instance; adjusting placement coordinates for alignment options; and generating a layout/hierarchical layout with placement circuit elements based on the calculated absolute placement coordinates.
申请公布号 US2012174051(A1) 申请公布日期 2012.07.05
申请号 US201213342228 申请日期 2012.01.03
申请人 WERNER TOBIAS T.;PARENT ANTHONY L.;POLIG RAPHAEL;WOERNER ALEXANDER;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 WERNER TOBIAS T.;PARENT ANTHONY L.;POLIG RAPHAEL;WOERNER ALEXANDER
分类号 G06F17/50 主分类号 G06F17/50
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