发明名称 |
BUILT IN SELF TEST FOR TRANSCEIVER |
摘要 |
An integrated circuit (IC), comprises a receiver on an IC substrate. The receiver is configured to receive a stressed input signal. A built in self test (BIST) circuit is provided on the IC substrate for testing the receiver. The BIST circuit comprises an encoder configured for receiving an input signal and identifying whether a first condition is present, in which two or more consecutive input data bits have the same polarity as each other. An output driver circuit provides the stressed input signal corresponding to the two or more consecutive input data bits. The stressed input signal has an amplitude that is larger when the encoder identifies that the first condition is present and smaller when the encoder identifies that two or more consecutive input data bits have different polarity from each other.
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申请公布号 |
US2012169361(A1) |
申请公布日期 |
2012.07.05 |
申请号 |
US20100981618 |
申请日期 |
2010.12.30 |
申请人 |
CHIEN JINN-YEH;ZHAN HAO-JIE;TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
CHIEN JINN-YEH;ZHAN HAO-JIE |
分类号 |
G01R31/3187 |
主分类号 |
G01R31/3187 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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