METHODE OF BUILDING CLOCK DISTRIBUTION PATH AND 3-DIMENSIONAL INTEGRATED CIRCUIT INCLUDING CLOCK DISTRIBUTION PATH

摘要

PURPOSE: A method for forming a clock distribution path and a 3D integrated circuit including the clock distribution path are provided to reduce system errors by decreasing a jitter and a skew of a clock signal distributed in a plurality of semiconductor layers. CONSTITUTION: A tri clock distribution path includes a first clock path(681), a second clock path(682), and a distribution path and transmits a clock signal. The first clock path comprises the first through silicon vias which pass through semiconductor chips and transmits a clock signal in a first direction. The second clock path comprise the second through silicon vias which pass through the semiconductor chips and transmits a clock signal in the first direction and a second direction. The distribution path connects the first clock path and the second clock path.