| 摘要 |
Signal synchronisers synchronise input signals with a clock signal. The input of each synchroniser is connected to a first input and the output of each synchroniser is connected to a second input of a respective first gate arrangement. The first gate arrangements provide an output signal only if there is an input signal on the first input and none on the second input or vice versa. The outputs of each of the first gate arrangements is connected to respective inputs of a second gate arrangement, which provides an output signal if there is a signal on any of its inputs. The output of the second gate arrangement is connected to a third gate arrangement which operates such that the clock signal to the synchronisers is only enabled when there is a change to the state of a signal received at the input of at least one of the synchronisers. |
