发明名称 |
Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
摘要 |
A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell. |
申请公布号 |
US8214778(B2) |
申请公布日期 |
2012.07.03 |
申请号 |
US20090497052 |
申请日期 |
2009.07.02 |
申请人 |
QUANDT JONATHAN R.;BECKER SCOTT T.;GANDHI DHRUMIL;TELA INNOVATIONS, INC. |
发明人 |
QUANDT JONATHAN R.;BECKER SCOTT T.;GANDHI DHRUMIL |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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