发明名称 |
Systems for total coverage analysis and ranking of circuit designs |
摘要 |
In some embodiments of the invention, a method and apparatus of consolidating all types of coverage metrics, obtained from an HDL simulator, under a single common framework is described. In other embodiments of the invention, a method and an apparatus are disclosed for performing ranking from a verification plan using total coverage metric. |
申请公布号 |
US8214782(B1) |
申请公布日期 |
2012.07.03 |
申请号 |
US201113014639 |
申请日期 |
2011.01.26 |
申请人 |
CHAKRABORTI SWAPNAJIT;PAGEY SANDEEP;GOMMERSHTADT BORIS;DUEK-GOLAN YAEL;CADENCE DESIGN SYSTEMS, INC. |
发明人 |
CHAKRABORTI SWAPNAJIT;PAGEY SANDEEP;GOMMERSHTADT BORIS;DUEK-GOLAN YAEL |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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