发明名称 AMPLIFICATORE OPERAZIONALE CON SOPPRESSIONE DEL LATCHING STATE
摘要 An embodiment of an amplifier circuit is proposed. The amplifier circuit includes an amplifier stage having at least one input terminal for receiving an input signal and at least one output terminal for providing an output signal being amplified with respect to the input signal. The amplifier circuit further includes a load stage of the amplifier stage, the load stage including at least one load node each one coupled with a corresponding one of the at least one output terminal. The amplifier circuit further includes a control block for providing a control signal to the load stage according to the output signal for regulating the output signal in feedback, and first biasing means for providing a first bias current to each load node through the amplifier stage. The load stage includes second biasing means for providing at least one second bias current to each load node and regulation means for providing a regulation current to each load node according to the control signal. In an embodiment, the amplifier stage includes separation means for replicating the first bias current into a separation current and for sinking the separation current from each load node, the amplifier circuit further including buffer means for providing a buffer current to each load node, the buffer current balancing the at least one second bias current and the regulation current at each load node.
申请公布号 ITMI20102437(A1) 申请公布日期 2012.06.30
申请号 IT2010MI02437 申请日期 2010.12.29
申请人 ACCENT S.P.A. 发明人 PELLEGRINI AURELIO
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