PURPOSE: A method for manufacturing a printed circuit board is provided to improve interlay conduction reliability by improving a junction between a via and a land which are simultaneously formed. CONSTITUTION: An inner circuit layer(130) is formed in a first insulation layer(110) through an electroplating process. The inner circuit layer includes a circuit pattern(135) and a pad unit(133). An inner via(125) is formed by plating the inside of the through hole. Both sides of a base substrate are coated with the first plating resist. An opening unit is formed by patterning the first plating resist to expose the pad unit. A metal post including a protrusion unit and a via(155) is formed from the exposed surface of the first plating resist.
申请公布号
KR20120069987(A)
申请公布日期
2012.06.29
申请号
KR20100131347
申请日期
2010.12.21
申请人
SAMSUNG ELECTRO-MECHANICS CO., LTD.
发明人
LEE, SUK WON;CHANG, TAE EUN;PARK, HO SIK;SOHN, KEUNG JIN