| 摘要 |
PURPOSE: A semiconductor memory device controlling a multi rank is provided to improve area efficiency by successively providing a rank signal synchronized with a clock. CONSTITUTION: A multi rank/slice control unit(120) provides a plurality of rank signals and a plurality of slice selection signals in response to a command, a clock, a chip selection signal, an MRS signal, and an address signal. A slice region comprises a plurality of slices controlled by the output of the multi rank/slice control unit. The multi rank/slice control unit includes a plurality of peri blocks and a multi rank peri control unit. |
