A NOR architecture for selecting a word line driver in a DRAM is disclosed. Complements of separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.
申请公布号
WO2012087473(A2)
申请公布日期
2012.06.28
申请号
WO2011US61607
申请日期
2011.11.21
申请人
INTEL CORPORATION;GHOSH, SWAROOP;SOMASEKHAR, DINESH;SRINIVASAN, BALAJI;HAMZAOGLU, FATIH
发明人
GHOSH, SWAROOP;SOMASEKHAR, DINESH;SRINIVASAN, BALAJI;HAMZAOGLU, FATIH