| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce delay elements constituting a pulse delay circuit without degrading the performance of a pulse phase difference encoding circuit. <P>SOLUTION: A counting section 3 for counting the laps of a pulse signal in a pulse delay circuit 2 comprises a plurality of sub counters (first and second counters 31, 32) connected in series such that the most significant bit output of the first counter 31 (lower sub counter) is an operation clock CK2 for the second counter 32 (higher sub counter). A second latch section 62 for latching a count value CNT2 of the second counter 32 is operationally delayed from a first latch section 61 for latching a count value CNT1 of the first counter 31 by a delay time ΔT1 in the first counter 31, which compensates a delay in the operation of the second counter 32 based on a delay in the first counter 31. <P>COPYRIGHT: (C)2012,JPO&INPIT |
