发明名称 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SUPPRESSING PEAK CURRENT
摘要 A memory cell array includes a plurality of memory cells, in which n (n is a natural number equal to 3 or larger) cells are simultaneously written. A control circuit controls the memory cell array. A conversion circuit converts data constituted of k (k is equal to n or smaller, and is a natural number equal to 3 or larger) bits stored in the memory cells into data of h (h is equal to k or larger, and is a natural number equal to 2 or larger) bits on the basis of a conversion rule.
申请公布号 US2012163078(A1) 申请公布日期 2012.06.28
申请号 US201213409329 申请日期 2012.03.01
申请人 SHIBATA NOBORU 发明人 SHIBATA NOBORU
分类号 G11C16/04 主分类号 G11C16/04
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