| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a reception circuit that reduces interpolation errors. <P>SOLUTION: The reception circuit includes: a sampling circuit (201) for sampling an input data signal according to a clock signal and outputting a sampling signal; a data interpolation circuit (202) for interpolating the sampling signal according to phase information about the sampling signal to the input data signal and outputting an interpolated data signal; an interpolation error decision circuit (203) for outputting an interpolation error based on the sampling signal and the phase information; a decision/equalization circuit (204) for equalizing the interpolated data signal with an equalization coefficient set on the basis of the interpolation error and deciding the equalized interpolated data signal to output a decision signal; and a phase detection circuit (205) for generating the phase information based on the decision signal or the equalized interpolated data signal and outputting the phase information to the data interpolation circuit and the interpolation error decision circuit. <P>COPYRIGHT: (C)2012,JPO&INPIT |
