发明名称 REDUCED PLATED THROUGH HOLE (PTH) PAD FOR ENABLING CORE ROUTING AND SUBSTRATE LAYER COUNT REDUCTION
摘要 Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate.
申请公布号 WO2012087552(A1) 申请公布日期 2012.06.28
申请号 WO2011US63348 申请日期 2011.12.05
申请人 INTEL CORPORATION;MALLIK, DEBENDRA;ROY, MIHIR K. 发明人 MALLIK, DEBENDRA;ROY, MIHIR K.
分类号 H01L23/48;H05K3/46 主分类号 H01L23/48
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