发明名称 DECODER AND DECODING METHOD
摘要 <P>PROBLEM TO BE SOLVED: To provide an LDPC decoder that has a memory with reduced capacity for storing probability messages. <P>SOLUTION: A decoder includes: a bit node processing unit which performs bit node processing in decoding processing of a cyclic-type LDPC code for each one-column block of a check matrix, and based on a probability message &alpha; in a one-column block, updates all probability messages &beta; in the one-column block; and a check node processing unit which performs sequentially and in stages calculation of check node processing of one row in calculation of check node processing of each row of the check matrix based on one probability message &beta; updated whenever one probability message &beta; in the one row is updated, and sequentially outputs a probability message &alpha; after update in the one row after all probability messages &beta; in the one row have been updated. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012124888(A) 申请公布日期 2012.06.28
申请号 JP20110239657 申请日期 2011.10.31
申请人 FUJITSU LTD 发明人 HAMAMINATO MAKOTO;YOSHIKAWA SHINPEI
分类号 H03M13/19 主分类号 H03M13/19
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