发明名称 GATE DRIVE VOLTAGE BOOST SCHEMES FOR MEMORY ARRAY II
摘要 Magnetic memory elements such as Phase Change RAM and Spin Moment Transfer MRAM require high programming currents. These high programming currents require high gate to source/drain voltages for the cell transistors controlling these programming currents, which can degrade the reliability of these cell transistors. This invention describes a circuit and method to write information into individual memory cells while minimizing the gate voltage stress in the cell transistors of the memory cells in which no information is being written. The circuit of this invention has a separately controllable word line voltage supply for each row of the memory array and a separately controllable voltage supply for each bit line of the memory array. During the write operation the voltage is raised for the word line of only one row of the array. The bit line voltages are then adjusted so that a 1 is written into the desired cells in that row and a 0 is written into the desired cells in that row.
申请公布号 EP2467853(A1) 申请公布日期 2012.06.27
申请号 EP20100810263 申请日期 2010.07.02
申请人 MAGIC TECHNOLOGIES INC. 发明人 YANG, HSU, KAI
分类号 G11C11/06 主分类号 G11C11/06
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