Latency counter, semiconductor memory device including the same, and data processing system

摘要

A latency counter includes an input selecting circuit that selects one of a plurality of signal paths and supplies an internal command to the selected signal path, a shift circuit that switches a correspondence relation between the signal paths and a latch circuit, and an output selecting circuit that causes the internal command taken in the latch circuit to be output. The input selection circuit includes a timing control circuit allocated to each of the signal paths. The timing control circuit includes an SR latch circuit that is set by the internal command and is reset in response to deactivation of a corresponding count value. Therefore, it becomes possible to suppress shortening of an active period of the internal command that is output from the input selecting circuit.