发明名称 FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 <p>PURPOSE: A method for fabrication a semiconductor integrated circuit device is provided to improve a processing amount of probe inspection by simultaneously inspecting a plurality of probes. CONSTITUTION: First and second metal layers(21A, 21B) are formed by sequentially laminating a rhodium film and an Ni film. First and second probes(7A, 7B) are projected in a square trapezoidal shape on a lower side of a thin film sheet in a metal layer. A through hole(24) is formed on a polyimide film between the metal layer and a wiring(23). The wiring and the metal layer are electrically connected through the through hole. The second metal layer on which the second probe is formed and a planar pattern of the through hole are made by rotating the first metal layer on which the first probe is formed and the planar pattern of the through hole by 180°.</p>
申请公布号 KR20120067977(A) 申请公布日期 2012.06.26
申请号 KR20120043994 申请日期 2012.04.26
申请人 RENESAS ELECTRONICS CORPORATION 发明人 OKAMOTO MASAYOSHI;HASEGAWA YOSHIAKI;MOTOYAMA YASUHIRO;MATSUMOTO HIDEYUKI;YORISAKI SHINGO;HASEBE AKIO;SHIBATA RYUUJI;NARIZUKA YASUNORI;YABUSHITA AKIRA;MAJIMA TOSHIYUKI
分类号 G01R1/06;H01L21/66;G01R1/067;G01R1/073;G01R3/00;G01R31/28;H01L21/822;H01L27/04 主分类号 G01R1/06
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