CPU data bus PLD/FPGA interface using dual port RAM structure built in PLD

摘要

A programmable logic device may include first and second ports in data communication with a memory block including a pair of address areas. A system using the programmable logic device may include the programmable logic device in data communication with a central processing unit and a controller. A method of using the programmable logic device may include generating a command from the central processing unit based on data read from one of the address areas and written to the second address area wherein the address areas are associated with a common memory address.