发明名称 |
Quick pixel rendering processing |
摘要 |
A three-dimensional (3D) graphics pipeline which processes pixels of sub-screens in the last stage (pixel rendering) in parallel and independently. The sub-screen tasks are stored in a list in a shared memory. The shared memory is accessed by a plurality of processing threads designated for pixel rendering. The processing threads seize and lock sub-screens tasks in an orderly manner and process the tasks to create the bit map for display on a screen. The tasks are created by dividing a display area having the vertex information superimposed thereon into M×N sub-screen tasks. Based on system profiling, M and N may be varied. |
申请公布号 |
US8207972(B2) |
申请公布日期 |
2012.06.26 |
申请号 |
US20060615379 |
申请日期 |
2006.12.22 |
申请人 |
WEI JIAN;WU CHEHUI;BROWN JAMES M;QUALCOMM INCORPORATED |
发明人 |
WEI JIAN;WU CHEHUI;BROWN JAMES M |
分类号 |
G06F15/00;G06F1/00;G06F9/46;G06F15/80;G06T1/20;G06T15/00 |
主分类号 |
G06F15/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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