发明名称 Live lock free priority scheme for memory transactions in transactional memory
摘要 A method and apparatus for avoiding live-lock during transaction execution is herein described. Counting logic is utilized to track successfully committed transactions for each processing element. When a data conflict is detected between transactions on multiple processing elements, priority is provided to the processing element with the lower counting logic value. Furthermore, if the values are the same, then the processing element with the lower identification value is given priority, i.e. allowed to continue while the other transaction is aborted. To avoid live-lock between processing elements that both have predetermined counting logic values, such as maximum counting values, when one processing element reaches the predetermined counting value all counters are reset. In addition, a failure at maximum value (FMV) counter may be provided to count a number of aborts of a transaction when counting logic is at a maximum value. When the FMV counter is at a predetermined number of aborts the counting logic is reset to avoid live lock.
申请公布号 US8209689(B2) 申请公布日期 2012.06.26
申请号 US20070854175 申请日期 2007.09.12
申请人 RAIKIN SHLOMO;GUERON SHAY;SHEAFFER GAD;INTEL CORPORATION 发明人 RAIKIN SHLOMO;GUERON SHAY;SHEAFFER GAD
分类号 G06F9/52;G06F7/00;G06F12/00;G06F13/00;G06F13/14 主分类号 G06F9/52
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