发明名称 Low power dual processor architecture for multi mode devices
摘要 A mobile computing device with multiple modes, for example, wireless communication and personal computing, has an application processor and a communication processor. In the computing mode, the application processor is the master processor. In the communication mode, the application processor is deenergized to conserve battery power, with the communication processor functioning as the master processor by accessing the device's peripheral bus using the memory interface of the communication processor.
申请公布号 US8208972(B2) 申请公布日期 2012.06.26
申请号 US20070946901 申请日期 2007.11.29
申请人 KRISHNAN RANGANATHAN;LUDWIN ALBERT S.;GARDNER WILLIAM R.;QUALCOMM INCORPORATED 发明人 KRISHNAN RANGANATHAN;LUDWIN ALBERT S.;GARDNER WILLIAM R.
分类号 G06F1/26;H04W52/02;G06F1/32;H04B1/16;H04B7/26;H04M1/73 主分类号 G06F1/26
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