发明名称 |
Hybrid time and frequency solution for PLL sub-block simulation |
摘要 |
A system for a fast method to simulate phase lock loop (PLL) sub-block simulation is presented. The simulation of the sub-blocks of the PLL involve solving a system of non-linear equations for the voltages and currents in the sub-blocks of the PLL. A harmonic balance method is used to solve the system of non-linear equation. The harmonic balance method involves creating a system of linear equations which is solved using a novel hybrid time and frequency domain preconditioner. The hybrid time and frequency domain preconditioner includes the strong and fast convergence property of time-domain preconditioning while avoiding the potential divergent problems of time-domain preconditioning. In addition the hybrid time and frequency domain preconditioner also includes the dependable convergence of frequency domain preconditioning while avoiding the potential stalling problems of frequency domain preconditioning. |
申请公布号 |
US8209154(B2) |
申请公布日期 |
2012.06.26 |
申请号 |
US20080112966 |
申请日期 |
2008.04.30 |
申请人 |
BOUARICHA ALI;SYNOPSYS, INC. |
发明人 |
BOUARICHA ALI |
分类号 |
G06F7/60;G06F17/10 |
主分类号 |
G06F7/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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