发明名称
摘要 A process and circuit for blending a foreground image (B) with a background image (A) , said foreground and background images being arranged in pixels and having color representations (R, G, B) . The foreground foreground image (A) has a transparency parameter (T(x,y)) in accordance with a so-called alpha plane representative of the transparency profile to apply to the foreground image. The process involves the steps of: - applying a dithering method on said alpha plane in order to convert said transparency parameter (T) into a one-bit transparency parameter (T'); - use said one-bit transparency parameter (T') for controlling a multiplexing unit having two inputs respectively receiving the foreground image (A) and the background image (B). In one embodiment, the one-bit transparency parameter T' into the two extreme values of a range of continuous values, for instance coded on 8 bits. The process then applies a four-pixel interpolation method to the foreground image (A) for the purpose of creating a five level transparency parameter in the blending process, and then uses the five level transparency parameter for controlling a multiplexing circuit for the purpose of achieving blending of the foreground image with the background image.
申请公布号 JP2012514263(A) 申请公布日期 2012.06.21
申请号 JP20110543994 申请日期 2009.12.29
申请人 发明人
分类号 G06T11/00;G06T15/50 主分类号 G06T11/00
代理机构 代理人
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