| 摘要 |
<P>PROBLEM TO BE SOLVED: To improve data transfer efficiency of a PCI device connected to a PCI express bus via a bridge. <P>SOLUTION: A bridge 1 is provided which connects a PCI express bus 2 and a PCI bus 6 to which memory data transfer protocols different from each other are specified. A cache line size copy-1 register 11 is provided which is mounted in a PCI device 7 connected to the PCI bus 6 and stores the same value as a cache line size-1 register 73 for storing a value to be referenced when a PCI device 7 requests memory read, and in which a value to be answered in place of the cache line size-1 register 73 is stored in response to an inquiry from a CPU 5 or the like to the cache line size-1 register 73. <P>COPYRIGHT: (C)2012,JPO&INPIT |
