| 摘要 |
<P>PROBLEM TO BE SOLVED: To output a reset signal in suitable timing with an inexpensive configuration. <P>SOLUTION: When an increase in voltage level of a hold voltage of a hold capacitor C input as a digital signal from an A/D conversion circuit 3 is detected, a comparator 5a finds the difference between voltage levels before and after the increase. When the found difference is equal to or less than a predetermined threshold, a reset signal is output. Therefore, the hold capacitor C is reset for the first time and the hold voltage is discharged at the point of time when the increment in hold voltage of the hold capacitor C accompanying input of an input signal Vin becomes equal to or less than the predetermined threshold suitable to saturation determination on the hold voltage. Consequently, the reset signal can be securely output at the point of time when the hold capacitor C is charged until the hold voltage reaches a value much closer to the peak value of the voltage level of the inversion signal of the input signal Vin than the hold voltage during first charging of the hold capacitor C. <P>COPYRIGHT: (C)2012,JPO&INPIT |
