| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a graphic arithmetic processing chip capable of suppressing fragmentation of a storage area by a simple algorithm whose load is suppressed. <P>SOLUTION: An on-chip memory 104 is divided into a plurality of sub-areas S which adjoin one another and are sectioned having data kinds of the same type respectively. Respective data in the sub-areas S are stored as respectively successive permutation data, which are stored to adjoin other permutation data. The data recorded in the respective sub-areas S differ in life cycle value as a period for which data is recorded in the on-chip memory 104, and sub-areas S including data having a short life cycle value are provided adjoining sub-areas S including data having a long life cycle value. <P>COPYRIGHT: (C)2012,JPO&INPIT |
