发明名称 |
INTER-DIE CONNECTION WITHIN AN INTEGRATED CIRCUIT FORMED OF A STACK OF CIRCUIT DIES |
摘要 |
<p>An integrated circuit is formed of a plurality of circuit dies 22, 24 having through silicon vias (TSVs) passing there-through. The placement patterns of the through silicon vias differ between the circuit dies. An inter-die routing layer is provided either in a face of a substrate of one of the circuit dies or in an outer face of a layer of processing circuitry of one of the circuit dies. The inter-die routing layer bridges the gaps between the vias and the connection points of different circuit dies. The inter-die routing layer may be formed of metal tracks.</p> |
申请公布号 |
WO2012082092(A1) |
申请公布日期 |
2012.06.21 |
申请号 |
WO2010US59996 |
申请日期 |
2010.12.13 |
申请人 |
ARM LIMITED;MCLAURIN, TERESA, LOUISE |
发明人 |
MCLAURIN, TERESA, LOUISE |
分类号 |
H01L25/065 |
主分类号 |
H01L25/065 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|