| 摘要 |
A DLL(Delay Locked Loop) circuit of a semiconductor memory device and a method for delaying and locking a clock therein are provided to control delay according to the variation of an operation voltage by increasing delay time of the clock when the operation voltage level increases and decreasing the delay time when the operation voltage level decreases. A voltage sensing unit(80) generates a sensing signal by sensing whether a delay unit operation voltage level exceeds a reference level. A delay unit(90) additionally controls the delay of an internal clock which is controlled by a delay control signal according to the enable of the sensing signal. The voltage sensing unit includes a comparison part comparing the levels of a first comparison voltage and a second comparison voltage, and a sensing signal driving part outputting the sensing signal by driving a signal outputted from the comparison part. |
