发明名称 |
Constructing a Clock Tree for an Integrated Circuit Design |
摘要 |
A method and apparatus for constructing a clock tree for an integrated circuit design is disclosed, the method comprising: extracting the path delays between the sequential devices in a placed netlist by performing timing analysis on the placed netlist; and constructing a clock tree for driving the sequential devices according to the path delays between the sequential devices so as to make the sum of the products of the timing delay between any two sequential devices and a clock tree branch weight of the two sequential devices minimum, wherein the clock tree branch weight of the two sequential devices is positively correlated with the number of clock tree levels from the branch point of the clock tree relative to the two sequential devices to the two sequential devices.
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申请公布号 |
US2012159416(A1) |
申请公布日期 |
2012.06.21 |
申请号 |
US201113325102 |
申请日期 |
2011.12.14 |
申请人 |
JIANG GUOFAN;LIN YI FAN;LIU YANG;YANG HAO;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
JIANG GUOFAN;LIN YI FAN;LIU YANG;YANG HAO |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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