| 摘要 |
<p>A semiconductor memory includes a sense amplifier (SA) which operates in response to activation of a sense amplifier enable signal (SAE) and determines logic held in a nonvolatile memory cell (MC) according to a voltage of a bit line (BL), the voltage varying with a cell current flowing through a real cell transistor, a replica cell transistor (RCT) coupled in series between a first node (NO1) and a ground line, and a timing generation unit (TGEN). The timing generation unit (TGEN) activates the sense amplifier enable signal (SAE) when the first node (NO1) coupled to the ground line via the replica cell transistor (RCT) changes from a high level to a low level. The replica cell transistor (RCT) includes a control gate receiving a constant voltage (VSA) and a floating gate coupled to the control gate. Thus, the activation timing of the sense amplifier (SA) can be optimally set in accordance with the electric characteristic of the memory cell. For resetting the bit lines (BL), all of the bit line selection switches are turned on to connect the bit lines (BL) to a common node (COM) which is pulled to the ground by a single reset switch controlled by a reset signal (RST).</p> |
