发明名称 |
SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF |
摘要 |
PURPOSE: A semiconductor package and a manufacturing method thereof are provided to reduce a load between different kinds of materials by minimizing an area ratio of a conductive material filling a through via. CONSTITUTION: A second redistribution layer(160) is electrically connected to one end of a via set(120). A semiconductor chip(210) is electrically connected to a first redistribution layer(150). A molding layer(250) is formed on a first dielectric layer(130) and the first redistribution layer. A molding layer covers up the semiconductor chip. A bump is connected to the second redistribution layer. |
申请公布号 |
KR20120064186(A) |
申请公布日期 |
2012.06.19 |
申请号 |
KR20100125301 |
申请日期 |
2010.12.09 |
申请人 |
NEPES CO., LTD. |
发明人 |
KANG, IN SOO;KWON, YONG TAE;PARK, BYUNG JIN |
分类号 |
H01L23/48;H01L21/60;H01L23/045;H01L23/055 |
主分类号 |
H01L23/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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