发明名称 |
Stack package having reduced electrical connection length suitable for high speed operations and method of manufacturing the same |
摘要 |
A stack package includes an upper semiconductor chip having a plurality of first bonding pads which are formed on an upper surface of the upper semiconductor chip and via-holes which are defined in the upper semiconductor chip under the respective first bonding pads; and a lower semiconductor chip attached to a lower surface of the upper semiconductor chip and having a plurality of second bonding pads which are formed on an upper surface of the lower semiconductor chip and bumps which are formed on the respective second bonding pads and are inserted into the respective via-holes to be come into the respective first bonding pads.
|
申请公布号 |
US8202762(B2) |
申请公布日期 |
2012.06.19 |
申请号 |
US201113218916 |
申请日期 |
2011.08.26 |
申请人 |
KIM SUNG MIN;SUH MIN SUK;HYNIX SEMICONDUCTOR INC. |
发明人 |
KIM SUNG MIN;SUH MIN SUK |
分类号 |
H01L21/60 |
主分类号 |
H01L21/60 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|