发明名称 INTEGRATED CIRCUIT CHIP AND FABRICATION METHOD
摘要 An integrated circuit chip includes a substrate die and integrated circuits and a layer incorporating a front electrical interconnect network formed on a front face of the substrate die. A local electrical connection via made of an electrically conductive material is formed in a hole of the substrate die. The via is linked to a connection portion of the electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via. A local external protection layer at least partly covers the electrical connection via and the electrical connection pillar.
申请公布号 US2012146226(A1) 申请公布日期 2012.06.14
申请号 US201113304823 申请日期 2011.11.28
申请人 STMICROELECTRONICS (CROLLES 2) SAS 发明人 CHAPELON LAURENT-LUC;CUZZOCREA JULIEN
分类号 H01L23/52;H01L21/768 主分类号 H01L23/52
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