PURPOSE: A multi-chip package manufacturing method is provided to prevent malfunction generated during a wire bonding process by supporting a non-overlapping region of a second semiconductor chip with a first semiconductor chip using an insulating layer. CONSTITUTION: A substrate includes a first bonding part and a second bonding part. A first semiconductor chip(130) connected to the first bonding part is formed on the upper surface of the substrate. An insulating layer(140) is formed on the upper surface of the substrate for surrounding side surfaces of the first semiconductor chip. A second opening part is formed by eliminating a part of the insulating layer for expositing the second bonding part. A second semiconductor chip which is wider than a first chip while being overlapped with the first chip on the first semiconductor chip and the insulating layer. The second bonding part is connected to the second semiconductor chip using a wire which passes the second opening part.
