| 摘要 |
A method for adding power gating to an integrated circuit design logic block that includes N-Nary dynamic logic (NDL) gates includes determining an initial number of power gating rows to add to the logic block. The logic block includes a number of rows of logic gates in which some of the rows include gates implemented as one of n NDL circuits, where n may be any positive integer. The method also includes determining a total power gating device width for all of the power gating rows, and determining a distribution of the power gating device width among a final number of power gating rows based upon a number of different clock phases used to clock the gates implemented as one of n NDL circuits. The method further includes placing the power gating rows within the logic block. |
