发明名称 FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 In the fabrication of a semiconductor integrated circuit device, a 2D-3D inspection technique for solder printed on a substrate is provided which permits easy preparation of data and easy visual confirmation of a defective portion. In a substrate inspecting step, first, a 3D inspection is performed, followed by execution of 2D inspection, whereby a 2D picked-up image of the portion of a pad determined to be defective can be displayed on a larger scale simultaneously with the end of inspection, thereby providing an environment for efficient visual confirmation of the defect. Further, by subjecting a raw substrate to measurement at the time of preparing inspection data, a relation between an original height measurement reference generated automatically by the inspection system and the height of a pad upper surface is checked, whereby it is possible to measure the height and volume of printed solder based on the pad upper surface.
申请公布号 US2012149136(A1) 申请公布日期 2012.06.14
申请号 US201213399684 申请日期 2012.02.17
申请人 发明人 WATANABE NORIO
分类号 G01B11/00;H01L21/66;G01N21/956;G06T1/00;H05K1/02;H05K3/34 主分类号 G01B11/00
代理机构 代理人
主权项
地址