CYCLE CUTTING WITH TIMING PATH ANALYSIS

摘要

The timing cycles in a circuit design are identified and cut, such that timing constraint paths in the circuit design are preserved. Timing cycles in the circuit design may be identified by traversing an adjacency list data structure, in which elements of the circuit design are represented as vertices interconnected by edges. Timing constraint paths may be distinguished from false timing paths using a greatest common path heuristic. Timing constraint paths may be marked as "constrained" to prevent these paths from being cut. With the cycles and timing constraint paths identified, cuts may be selected that cut the identified timing cycles, while preserving the timing constraint paths. The cycle cuts allow the circuit design to be correctly processed within a conventional CAD tool design flow.