POWER/GROUND LAYOUT FOR CHIPS

摘要

Embodiments of the present disclosure provide a chip that comprises a base metal layer (102) formed over a first semiconductor die (104) and a first metal layer (110) formed over the base metal layer. The first metal layer includes a plurality of islands (112) configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer (118) formed over the first metal layer. The second metal layer includes a plurality of islands (120) configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.