| 摘要 |
Apparatuses, circuits, methods, and other embodiments associated with digital power on reset are described. In one embodiment, an apparatus is implemented with a digital electronic component that produces a clock signal. The apparatus also includes a first counter that outputs a first count signal based on the clock signal and a second counter that outputs a second count signal based on the clock signal. The apparatus also includes a power on reset logic that selectively provides a power on reset signal based on the first count signal and the second count signal. The power on reset logic can also selectively disable the apparatus upon providing the power on reset signal. |
